Forums :: Resources :: Features :: Photo Gallery :: Vintage Radio Shows :: Archives :: Books
Support This Site: Contributors :: Advertise


It is currently Sep Sun 23, 2018 6:17 am


All times are UTC [ DST ]





Post New Topic Post Reply  [ 15 posts ] 
Author Message
 Post subject: Help with J-fet output impedance
PostPosted: Feb Tue 20, 2018 9:14 am 
Member

Joined: Aug Sat 13, 2016 6:03 am
Posts: 120
First off let me say I'm a tube guy. Most solid state stuff is magic to me. I'm designing a simple balanced input unbalanced output RF amp using MFP-102 J-fets. This is a common source configuration with a hi impedance input into the fets. All I have been able to discover after too many hours of research on the web is the output impedance on the MPF-102 is listed as low to moderate. OK, fine. So can anyone give me a ballpark idea on an actual number? It would be really helpful to determine the turn ratio on the output balun I need to wind. I know I could just experiment with this, but it would be nice to have a starting point. Thanks in advance for any insight you might be able to provide. michael


Top
 Profile  
 
 Post subject: Re: Help with J-fet output impedance
PostPosted: Feb Tue 20, 2018 12:54 pm 
Member

Joined: Sep Tue 30, 2014 6:08 am
Posts: 3041
Location: The Old Dominion VA 23518
Well, the Rds (Drain-Source resistance) range for the MPF102 is 100 ohms to 500 ohms, so direct output impedance is somewhere within that range, assuming a low impedance power source. Add any other circuit elements (Drain or Source connected resistances), nodes, or feedback paths, and that would change.

I don't think I've ever seen a JFET drive an inductance directly - most circuits add a transistor to act as a follower to lower the output impedance.

Attachment:
FET wideband.gif
FET wideband.gif [ 20.74 KiB | Viewed 1231 times ]


The FET used above is the same "process" as the MPF102 (process 50, per National Semi Discrete Databook).

It's been a while since i designed anything RF, so others please chime in...

_________________
Brian
"Capacitor Cosmetologist since 1979"
USN Retired 1984-2006 (Avionics/Cal)


Top
 Profile  
 
 Post subject: Re: Help with J-fet output impedance
PostPosted: Feb Tue 20, 2018 3:00 pm 
Member
User avatar

Joined: Jul Mon 26, 2010 8:30 pm
Posts: 23374
Location: Annapolis, MD
Here is a comprehensive data sheet for a general purpose JFET:
http://www2.eng.cam.ac.uk/~dmh/ptialcd/jfet/2N3819.pdf

The drain curves look a lot like what we are used to seeing in Pentodes. The typical parameter for the drain is the output conductance, gos. This is the inverse of the plate resistance typically given for pentodes. For the device in the data sheet, gos is given as 25micro-Siemens, which converts to 40kohms ( quite pentode-like )
As with pentodes, the typical load resistance will normally be much less than 1/ gos (Rp for a pentode)
It seems to me that the design process would be similar...i.e. Find a load that gives best performance and wind a transformer to convert the actual load accordingly.

PS: I think if you want really low output impedance from a FET, you'd use a source-follower.

_________________
-Mark http://pixellany.com

"It's always something". --Gilda Radner (1946 - 1989)


Top
 Profile  
 
 Post subject: Re: Help with J-fet output impedance
PostPosted: Feb Tue 20, 2018 10:16 pm 
Member

Joined: Sep Tue 30, 2014 6:08 am
Posts: 3041
Location: The Old Dominion VA 23518
Here's the MIT Open Courseware summary table for JFET amplifiers - not knowing the OP's configuration, I can see now the confusion....

Attachment:
jfet.gif
jfet.gif [ 38.49 KiB | Viewed 1199 times ]


Me, if I was designing a JFET amp, I'd relent and use a known circuit - plenty out there, especially with the OP's RF-friendly MPF102:

https://archive.org/search.php?query=MPF102&sin=TXT

Ham Radio magazine has a nice article in the Feb 1976 issue (Page 19...) with some nice circuits and applications for each:

https://www.google.com/url?sa=t&rct=j&q ... 201976.pdf

Rufus Turner's JFET book also has some nice buildng blocks. I have the paperback copy.

And, of course, the Markus Electronic Circuits Reference Manual has a nice assortment as well, albeit without an inductance/balun as a load....

_________________
Brian
"Capacitor Cosmetologist since 1979"
USN Retired 1984-2006 (Avionics/Cal)


Top
 Profile  
 
 Post subject: Re: Help with J-fet output impedance
PostPosted: Feb Wed 21, 2018 7:58 am 
Member

Joined: Aug Sat 13, 2016 6:03 am
Posts: 120
I read all your links Mark and Brian and came away with a couple more pieces to my puzzle. I do have a known circuit and plan to copy it but, it is unbalanced. Next I'll make a mirrored image of it and run it push-pull. The reason for the balun is to combine the 2 inputs and give me one 75 ohm output. Let me simplify my original question. I know that 50 ohms of impedance is considered to be low. If so, as you increase this....when is it considered to be high ?


Top
 Profile  
 
 Post subject: Re: Help with J-fet output impedance
PostPosted: Feb Wed 21, 2018 9:04 am 
Member
User avatar

Joined: Jul Mon 26, 2010 8:30 pm
Posts: 23374
Location: Annapolis, MD
Thanks to Brian for all the stuff I couldn't find....;)

Very often in circuit design, you have situations where "low" or "high" simply mean that the parameter in question is low enough or high enough to allow simplification of the equations. This is highlighted in the table that Brian posted.

In RF circuits, we typically have a requirement to match a transmission line. Ideally, this means that the line is terminated at both ends with a resistive load at its characteristic impedance. ( let's assume 50 ohms). However, it is often "good enough" to drive a line from a source that is near 50 ohms, and terminate the other end with exactly 50 ohms**.

I think an amplifier driving a 50-ohm line favors an inherently low impedance topology....eg, in S/S parlance, an emitter- or source-follower. One approach is to make the gain stage output impedance as low as possible, and then add series resistance to match the line.

Some googling with terms like "driving transmission lines" will help get you past my arm-waving......


** ideally, you only have to match one end of a transmission line. With a perfect line and a perfect load, there is no reflection from the load end. In the real world, of course, there is a reflection....therefor you also terminate st the driving end to minimize the reflection of the reflection........say that 5 times fast....;)

_________________
-Mark http://pixellany.com

"It's always something". --Gilda Radner (1946 - 1989)


Top
 Profile  
 
 Post subject: Re: Help with J-fet output impedance
PostPosted: Feb Wed 21, 2018 6:15 pm 
Member

Joined: Sep Tue 30, 2014 6:08 am
Posts: 3041
Location: The Old Dominion VA 23518
michael w wrote:
I read all your links Mark and Brian and came away with a couple more pieces to my puzzle. I do have a known circuit and plan to copy it but, it is unbalanced. Next I'll make a mirrored image of it and run it push-pull. The reason for the balun is to combine the 2 inputs and give me one 75 ohm output. Let me simplify my original question. I know that 50 ohms of impedance is considered to be low. If so, as you increase this....when is it considered to be high ?


Couldn't you just combine, then amplify? You could do it building block style very easy with some Mini-Circuit stuff, and skip the design stage altogether....

https://www.minicircuits.com/WebStore/Splitters.html <- Splitter/combiners

https://www.minicircuits.com/WebStore/Amplifiers.html <- Amps

Of course, knowing what you are attempting to make is still a mystery, but that's your prerogative.


There's a mantra I follow with RF stuff - if Mini-Circuits doesn't make it, some Ham homebrewer does.

The only corollary is that if the Ham homebrewer shared his circuit, the Chinese will sell the finished product to you for postage.

_________________
Brian
"Capacitor Cosmetologist since 1979"
USN Retired 1984-2006 (Avionics/Cal)


Top
 Profile  
 
 Post subject: Re: Help with J-fet output impedance
PostPosted: Feb Wed 21, 2018 6:43 pm 
Member
User avatar

Joined: Jul Mon 26, 2010 8:30 pm
Posts: 23374
Location: Annapolis, MD
Some engineers use only circuits that they designed...especially if they were able to patent it. Others never design anything if they can just copy something.

The latter are normally much more productive, but only if they know what they are doing. Copying something without understanding how it works is often not a good plan......

_________________
-Mark http://pixellany.com

"It's always something". --Gilda Radner (1946 - 1989)


Top
 Profile  
 
 Post subject: Re: Help with J-fet output impedance
PostPosted: Feb Thu 22, 2018 9:34 am 
Member

Joined: Aug Sat 13, 2016 6:03 am
Posts: 120
The latter are normally much more productive, but only if they know what they are doing. Copying something without understanding how it works is often not a good plan...... I'm still LOL mark. Been there and trying to do that.
Brian, this whole project is meant to be really simple. I have a loop antenna for 80m that needs some amplification to really make it right. What I would like to do is place a J-fet amp (MPF-102) on each end of the loop. The output balun with 2 primary bifilar windings take the two output signals from the fets and combine them into a single coax connector. That's all there is to the circuit and I have that part figured out. There are many to copy. I was just hoping that someone could give me a starting point as to how many turns to put on the primary side of the balun. Thank you Brian, because in all the information you refered me to, I stumbled across a diagram where someone took a MPF-102 and built what I was looking for. I was fortunate that he noted the number of turns on his balun so I'm home free. Thank you both for all your time helping me here. You've shown me some great links that I want to read if I ever get some time.


Top
 Profile  
 
 Post subject: Re: Help with J-fet output impedance
PostPosted: Mar Thu 15, 2018 9:49 am 
Member
User avatar

Joined: Jun Fri 20, 2014 7:10 pm
Posts: 865
I think that this is a tricky question because the output transformers used in those loop preamp designs are NOT matching the JFET drain impedance (ro) to the transmission line. Or, as one engineer who later went on to become a professor told me, an impedance-transforming network (in this case a broad-band transformer) is often placed between an active device and a transmission line, but this is not necessarily an impedance-matching network.

The turns ratios in the amplifier circuits that I'm seeing, I believe, were selected empirically. The gain was set to be just high enough to make background electrical/atmospheric noise audible. Having much more gain than that would not bring in additional stations; in fact, it might be counter-productive because it might cause overload. Another risk of presenting too high an impedance to the FET drains is circuit instability. For a pair of MPF-102s, I would recommend, as a starting point, that an impedance of 2000 Ohms be presented between the drains.


Top
 Profile  
 
 Post subject: Re: Help with J-fet output impedance
PostPosted: Mar Fri 16, 2018 1:32 am 
Member

Joined: Aug Thu 06, 2015 2:20 am
Posts: 137
Please correct me if I'm saying something which is not correct, but isn't the FET a current source and if its output is taken from the Drain isn't its output impedance determined primarily by the resistor connected from the Drain to Vcc?


Top
 Profile  
 
 Post subject: Re: Help with J-fet output impedance
PostPosted: Mar Fri 16, 2018 1:59 am 
Member
User avatar

Joined: Sep Mon 16, 2013 2:42 am
Posts: 2818
Location: Tucson, Arizona U.S.A.
Quote:
Well, the Rds (Drain-Source resistance) range for the MPF102 is 100 ohms to 500 ohms

Not knowing where this came from, these values sound like the minimum source to drain resistance that is possible when using the FET as a switch. When used as an amplifier, the impedance will be considerably higher.

Quote:
I have a loop antenna for 80m that needs some amplification to really make it right. What I would like to do is place a J-fet amp (MPF-102) on each end of the loop.

So the center tap of the loop will be grounded? The gates of FETs require a return circuit just like the grids of tubes do.

Quote:
I was fortunate that he noted the number of turns on his balun so I'm home free.

Only if you use the same core that he used.

_________________
Jim Mueller


Top
 Profile  
 
 Post subject: Re: Help with J-fet output impedance
PostPosted: Mar Fri 16, 2018 11:33 pm 
Member
User avatar

Joined: Jun Fri 20, 2014 7:10 pm
Posts: 865
Here is a generic set of characteristic curves for a JFET:

Attachment:
JFET.JPG
JFET.JPG [ 21.6 KiB | Viewed 886 times ]


As the diagram shows, in the "Ohmic region" the channel acts like a resistor. For a small signal FET like an MPF102, this is a few hundred Ohms. For a power MOSFET, this value could be just a few milli-Ohms. Outside of the Ohmic region, the transistor starts to act like a current source. When building a linear amplifier stage, you do not want your transistor to go into the Ohmic region because the signal will clip here.

Quote:
So the center tap of the loop will be grounded? The gates of FETs require a return circuit just like the grids of tubes do.


He definitely needs a DC return for the gates. He could do this one of several ways:

  • Connect the FET gates directly to the loop and ground the center tap (this will provide the best common-mode rejection and highest Q)
  • Connect the FET gates directly to the loop and DC return one end through approximately 100k - 470k (this value needs to be found empirically; if it is too high, 60 Hz hum may ride in on all received stations)

Quote:
I was fortunate that he noted the number of turns on his balun so I'm home free.


His output transformer design might work well for his receiver, but that does not necessarily mean that it will work for everyone. Not all radios present 50 Ohms to the antenna. You may have to adjust the turns ratio.


Top
 Profile  
 
 Post subject: Re: Help with J-fet output impedance
PostPosted: Mar Sat 17, 2018 9:29 am 
Member

Joined: Aug Sat 13, 2016 6:03 am
Posts: 120
Thanks Alfredo and all the rest who have replied. I did find that load line graph, and plan to use it. From all of your comments I believe I have enough information to get started on winding this toroid. I'm sure I'll be doing some experimenting when I get it operational.


Top
 Profile  
 
 Post subject: Re: Help with J-fet output impedance
PostPosted: Mar Sun 18, 2018 1:59 pm 
New Member

Joined: Sep Sat 12, 2015 1:51 am
Posts: 1
Let me add here that individual devices vary as much as 3:1 in their characteristics (at least MOSFETs do). Also, depending on actual frequencies encountered in your "wideband" application, there exist parasitic capacitances at the drain and source nodes. One thing that may help is if your ultimate load, be it t-line or whatever, is resistive, then to a first order the load impedance encountered at the buffer will be predominantly resistive (given appropriate choice of wideband magnetics).

You might prototype an MPF-102 buffer and load it with a few different resistances and test it across your bandwidth of interest. The results might help you to deduce the output impedance of the buffer.

Best wishes on your experiments,
Coop, aa1ww


Top
 Profile  
 
Post New Topic Post Reply  [ 15 posts ] 

All times are UTC [ DST ]


Who is online

Users browsing this forum: No registered users and 3 guests



Search for:
Jump to:  
























Privacy Policy :: Powered by phpBB