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 Post subject: Outputs treatment with a CD4060
PostPosted: Sep Mon 06, 2021 9:58 pm 
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My frequency synthesizer uses a CD4060 oscillator to generate the 10KHz steps. It works great. Several of us have built and used the circuit with 100% success IIRC.

However, a noise problem has developed on a board I'm developing. I plan to have a few of these boards made and give away to members who want to try a 386 based transmitter with synthesized frequencies. A noise problem develops when I shrink the board to fit both the synth and the 386 components. It's an intermittent oscillation somewhere around 700 Hz. In can be cured by bypassing either pin 4 or pin 5 (Q6 and Q5) to ground on the CD4060. I want to understand the source of this oscillation, as it's never been a problem before. My first suspicion is the cramming together of traces in an RF rich environment causes unwanted feedback into the 4060.

The board I'm working with had single side copper. I made a ground plane out of insulated aluminum foil positioned on the trace side of the board. Thus it's separated from the board by at least the length of the component stubs. I was able to track down at least one source causing this problem by pushing the ground plane toward the board in different places, one of which quieted the oscillation.

Now it may be the problem will solve itself when I have the pros make the board with double sided copper so it has a proper ground plane. Maybe not. For now I want to understand how to treat those unused outputs.

Common practice is to ground all unused inputs and leave unused outputs floating. That's what I did in the circuit (schematic below). Pins 1-7 correspond respectively to Q12, Q13, Q14, Q6, Q5, Q7, Q4. The 10KHz output is taken off Pin 15, which is Q10.

Bypassing either Q5 or Q6 with .047 to ground kills the oscillation. Bypassing Q4 creates a sustained appx 700 Hz oscillation. Bypassing Q7 produces a rough rushing sound.

I could just solve the problem and put a cap on Q5 or Q6. But I want to understand what's happening and to learn what is best practice for dealing with this kind of problem. Thanks for any help.


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 Post subject: Re: Outputs treatment with a CD4060
PostPosted: Sep Tue 07, 2021 1:25 am 
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No idea what's going on but the board should be double sided copper and ugly bug construction is better. Try isolating the 4060 from V+ supply with a 1mH choke and add two more Decoupling capacitors of values 4.7u and 100n very near to the IC. Then let me know if the problem is solved.


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 Post subject: Re: Outputs treatment with a CD4060
PostPosted: Sep Tue 07, 2021 1:33 am 
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When you get the Bug's worked out. Put me down for one of the boards, Please.


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 Post subject: Re: Outputs treatment with a CD4060
PostPosted: Sep Tue 07, 2021 5:17 am 
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Dare4444 wrote:
No idea what's going on but the board should be double sided copper and ugly bug construction is better. Try isolating the 4060 from V+ supply with a 1mH choke and add two more Decoupling capacitors of values 4.7u and 100n very near to the IC. Then let me know if the problem is solved.


Thanks for the suggestions! Here's the board so far. in deed I'm finding I'm needing a lot more decoupling caps than expected. Circled in white are the two caps currently at the power input of the 4060. There's the 100n right at the power pin and a 100uf adjacent that also serves to smooth the rest of the board.

I fed the power through a 1 mH choke directly to pin 16 of the 4060 and I added the 4.7 uF there. No difference. Other than adding caps to the unused outputs, it seems pushing up the ground plane makes the most difference. I guess I'll have get some double sided to see if that really solves the problem, but UGH, lining up the holes would be an etching bi---, uh, challenge.

BTW, the weird RF output transistor traces are so different transistor pinouts can be used. Ditto for the traces that would contain appropriate resistors and caps. The board will be useful for two versions, FET and bipolar.


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 Post subject: Re: Outputs treatment with a CD4060
PostPosted: Sep Tue 07, 2021 12:05 pm 
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I am not smart enough to help with the problem, but I wouldn’t mind one of the boards when you get it sorted. I built the stand alone synthesiser and it worked very well, but it would be nice to have it and the TX on the same board.


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 Post subject: Re: Outputs treatment with a CD4060
PostPosted: Sep Tue 07, 2021 12:36 pm 
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I think we have talked about this type of issue before.

If you do what you are planning, with a ground plane on the pcb top and plated through holes would be ok, then wherever a component pin connects to ground, it is on the ground plane , it likely will be fine.

I would make most of the power supply bypass caps from the power supply distribution to the ground plane 0.1uF monolithic ceramic types, rather than 0.01uF, because of the frequency range over which your circuit is operating.


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 Post subject: Re: Outputs treatment with a CD4060
PostPosted: Sep Tue 07, 2021 2:41 pm 
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I believe you can leave pin 12 of the cd4046 floating. Your schematic shows it floating but there is a trace and a 100k resistor from trace to ground on the actual board. That pin is optionally used to "offset" the PLL's oscillator frequency. (AC or DC current drawn from it will shift the oscillator's frequency.) Unsolder pin 12 and pull it far enough out of its hole to guarantee it is disconnected from its pcb trace (which makes a dandy antenna to pick up noise from the nearby Q4,5,6,7 pins). Consider leaving the pin floating and replace the board's 100k resistor with a jumper, which will ground the trace in question and perhaps further isolate the nearby unused 4060 outputs.

If that doesn't help, next look at shielding the 10.24mHz crystal and nearby components, particularly the 22pF and 47pF capacitors. They also serve as wonderful noise pickups. In any case, grounding outputs from the divider chip doesn't seem like the best fix if the actual problem can be solved.

BTW, when I experimented with this circuit a couple of years ago I experienced quieter pll phase noise (resulting in lower hiss in the broadcasted audio) with a different value cap in series with the 1k resistor connected to the 4046 pin 9. Without part numbers to refer to, I hope this makes sense. I used 10uF instead of 100nF, and I used tantalum to keep leakage as low as possible. 10uF was overkill, 1uF works nearly as well to smooth out more ripple on the VCO's control voltage without killing its lockup ability. The pll's lockup time is a wee bit slower after the change but still more than adequate within the frequency range.

Also BTW, have you re-checked the final output frequency? The values of the 22pF/47pF caps next to the crystal could be larger than necessary. You might need to reduce the 47pF value if the output frequency is a bit low. Cap values are determined in part by a crystal's spec'd capacitance load, which is stated in its spec sheet. Using the formula CL = (C1 * C2) / (C1 + C2) + Cstray, where CL is the value from the spec sheet, you can design values for the two capacitors (which are usually the same). I just plug in 5pf for a Cstray value. (** see edit below) A pair of 20pF caps would be a good match for a modern 18pf crystal. One of those caps can be a trimmer to provide for frequency adjustment. If the overall capacitance amount is too high, the oscillator frequency will be lowered and in extreme cases, the oscillator may not start by itself. Obviously, your values work as long as the final frequency is not too low.

**edit: C1 and C2 are the capacitor's actual pF value PLUS additional pF of whatever is connected. For example, the cd4060 data sheet shows a typical pF value of 5 for each pin. This amount is effectively added to each capacitor's value. There is additional stray capacity from pcb traces which should be considered and is added directly to the overall pF load, and 5pf is reasonable for a few short pcb traces. Point to point wiring would be a larger amount of course. So, to pick values for a crystal cut for 18pF, a pair of 20pF caps should work well as determined by trail of standard values into the formula and picking the result closest to 18pF. A pair of 20pf caps for C1 and C2 are entered into the formula each as 25 (20 for the capacitor + 5 for the associated IC pin). Cstray is entered as 5. The equation becomes (25*25)/(25+25) + 5. The answer is 17.5, which is close to the 18pF target value.

_________________
-Richard


Last edited by richfair on Sep Wed 08, 2021 2:18 pm, edited 1 time in total.

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 Post subject: Re: Outputs treatment with a CD4060
PostPosted: Sep Tue 07, 2021 3:40 pm 
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Perhaps the ICs are too close together?


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 Post subject: Re: Outputs treatment with a CD4060
PostPosted: Sep Tue 07, 2021 5:08 pm 
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You guys rock! THANKS for excellent ideas.

I have left pin 15 floating in previous circuits and added the resistor only due to "good practice." I'm sure we've all experienced conflicts with "good practice" and practical reality.

richfair wrote:
Also BTW, have you re-checked the final output frequency? The values of the 22pF/47pF caps next to the crystal could be larger than necessary. You might need to reduce the 47pF value if the output frequency is a bit low. Cap values are determined in part by a crystal's spec'd capacitance load, which is stated in its spec sheet. Using the formula CL = (C1 * C2) / (C1 + C2) + Cstray, where CL is the value from the spec sheet, you can design values for the two capacitors (which are usually the same). I just plug in 5pf for a Cstray value. A pair of 20pF caps would be a good match for a modern 12pf crystal. One of those caps can be a trimmer to provide for frequency adjustment. If the overall capacitance amount is too high, the oscillator frequency will be lowered and in extreme cases, the oscillator may not start by itself. Obviously, your values work as long as the final frequency is not too low.


Good eye you have. I've been using a 5-60 pF trimmer for the 47 pF. It adjusts frequency roughly +-100Hz, so I'm going with it, as it gets the frequency within 1-2 Hz.

Dare4444 wrote:
Perhaps the ICs are too close together?


That's quite possible. The original synth worked fine with no ground plane and the ICs had plenty of clearance. I've built two iterations so far with the ICs close together, one without the LED indicator, the other with. For abovementioned reasons, neither has a ground plane. The first performs flawlessly. The second that has the LED circuitry and other changes is the noisy one. I'll check that again, as the green feed line to the LED is currently a wire on top of the board that runs right by the 4060. I'll check its position and bypassing. If I can get this to quiet without a proper ground plane, as I've experienced up to now, it should be bulletproof with one. Stay tuned, literally...


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 Post subject: Re: Outputs treatment with a CD4060
PostPosted: Sep Wed 08, 2021 4:45 pm 
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Seems to me that a 700Hz signal would have to originate from the audio/modulator part of the circuit. Do you have a scope? It would likely be a big help in tracing the source of the 700Hz signal. LM386's and other power audio IC's are notorious for creating interference with other circuitry, due to signal coupling into the power supply lines. It's best to feed power to the LM386 with separate traces connected directly back to the power connection point on the PCB, and try to keep the LM386 as electrically isolated as possible from the rest of the circuit. The LM386 datasheet has layout recommendations in section 11.
https://www.ti.com/lit/ds/symlink/lm386 ... g.com%252F
Also, as Acornvalve noted, the use of 0.1µF bypass caps is the norm.


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 Post subject: Re: Outputs treatment with a CD4060
PostPosted: Sep Wed 08, 2021 6:23 pm 
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BobWeaver wrote:
Seems to me that a 700Hz signal would have to originate from the audio/modulator part of the circuit. Do you have a scope? It would likely be a big help in tracing the source of the 700Hz signal. LM386's and other power audio IC's are notorious for creating interference with other circuitry, due to signal coupling into the power supply lines. It's best to feed power to the LM386 with separate traces connected directly back to the power connection point on the PCB, and try to keep the LM386 as electrically isolated as possible from the rest of the circuit. The LM386 datasheet has layout recommendations in section 11.
https://www.ti.com/lit/ds/symlink/lm386 ... g.com%252F
Also, as Acornvalve noted, the use of 0.1µF bypass caps is the norm.


A first check using .1 uF to bypass at the power supply rails of each IC makes no difference. Last night I tried adding some additional ground plane on the component side very close to the 4060. No difference. I can try the 386 separate power line by lifting the power pin, easy because while in development IC sockets are employed. They may have the unintended effect of lifting the ICs too far from the ground plane.

Perhaps the best approach is to get some double sided copper clad and etch a third prototype with ground plane. I would still use sockets, though. Small traces can be added to bypass those 4060 pins if needed and if not, then all the better.

Here's a video so you can hear the noise and how only the added cap removes it (so far). No need to complain about the 60Hz hum. It's ever present in this room, which is why my final tests are always outside on the deck, away from the annoying source.

https://youtu.be/9l-Z4_nFTk4

EDIT: Upon further checking, I'm suspecting that the noise is jitter or chatter affecting the PLL, as an additional source of noise modulation.

I've found that bypassing 4060 output pin that feeds the 10KHz square wave to the PLL also removes the noise. It clears up the noise whether connected to ground or V+. Pin 15 output on the 4060 scopes a nice square wave with rounded corners and is not affected by a 100 pF cap to V+ or ground. If V+ it's not bypassing directly to ground, but either way it's convenient and works. For now I'm going with that.

Although I do want to understand what's going on with that 4060 that cleans the noise when any one of four outputs is bypassed, for now I'm going to go with adding a 100pF to the board where there's plenty of room for it. If needed, fine, if not, fine. Thanks for the help!


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 Post subject: Re: Outputs treatment with a CD4060
PostPosted: Sep Sat 11, 2021 12:38 pm 
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CD4060.. Hmm interesting. Perhaps its pins are radiating square waves and grounding it with a capacitor stops the radiation. I faced similar problem with my PLL FM TX where these tones and noises were constantly being heard on the TX signal due to the CD4060 crystal oscillator being close to other ICs and oscillator circuitry. Keeping them far away solved it, using RFC and capacitor decoupling for the CD 4060 and RF oscillator prevented mixing of the tones from 4060 via the power line.


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 Post subject: Re: Outputs treatment with a CD4060
PostPosted: Sep Sat 11, 2021 2:06 pm 
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If ever you view what appears to be a sharp or fast rise square wave on a scope, likely the upper frequency components are 23 x the fundamental. This is one problem with digital signals. Even simple systems that send digital data down cables, turn the cables into radio transmitters that plaster interference all over the MW and SW radio bands. Any radio apparatus, be it transmitters or receivers, with digital switching circuits nearby, tend to have interference issues for this reason and shielded enclosures and good earthing for the digital part get critical. The capacitor you added is acting like an integrator and slowing the rise & fall times of the switching signals, and hence lowering the interference. Ideally the frequency synthesizer part is in a shielded box and its output is passed though an LPF to get rid of the high frequency harmonics, but that is less useful if your RF output stage is a switching design and requires square wave drive.


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 Post subject: Re: Outputs treatment with a CD4060
PostPosted: Sep Sat 11, 2021 3:00 pm 
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ACORNVALVE wrote:
If ever you view what appears to be a sharp or fast rise square wave on a scope, likely the upper frequency components are 23 x the fundamental. This is one problem with digital signals. Even simple systems that send digital data down cables, turn the cables into radio transmitters that plaster interference all over the MW and SW radio bands. Any radio apparatus, be it transmitters or receivers, with digital switching circuits nearby, tend to have interference issues for this reason and shielded enclosures and good earthing for the digital part get critical. The capacitor you added is acting like an integrator and slowing the rise & fall times of the switching signals, and hence lowering the interference. Ideally the frequency synthesizer part is in a shielded box and its output is passed though an LPF to get rid of the high frequency harmonics, but that is less useful if your RF output stage is a switching design and requires square wave drive.


Wow. So much to learn from you. Could you please share the schematic of optical isolator again? It was lost when the thread was deleted.


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 Post subject: Re: Outputs treatment with a CD4060
PostPosted: Sep Sat 11, 2021 3:53 pm 
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Dare4444 wrote:
CD4060.. Hmm interesting. Perhaps its pins are radiating square waves and grounding it with a capacitor stops the radiation. I faced similar problem with my PLL FM TX where these tones and noises were constantly being heard on the TX signal due to the CD4060 crystal oscillator being close to other ICs and oscillator circuitry. Keeping them far away solved it, using RFC and capacitor decoupling for the CD 4060 and RF oscillator prevented mixing of the tones from 4060 via the power line.


Well I guess I'm glad that you had problems with the CD4060, as you solved them and that sheds light on the problem I was having.

ACORNVALVE wrote:
If ever you view what appears to be a sharp or fast rise square wave on a scope, likely the upper frequency components are 23 x the fundamental. This is one problem with digital signals. Even simple systems that send digital data down cables, turn the cables into radio transmitters that plaster interference all over the MW and SW radio bands. Any radio apparatus, be it transmitters or receivers, with digital switching circuits nearby, tend to have interference issues for this reason and shielded enclosures and good earthing for the digital part get critical. The capacitor you added is acting like an integrator and slowing the rise & fall times of the switching signals, and hence lowering the interference. Ideally the frequency synthesizer part is in a shielded box and its output is passed though an LPF to get rid of the high frequency harmonics, but that is less useful if your RF output stage is a switching design and requires square wave drive.


Makes sense, thanks. The square wave from the CD4060 does have a sharp rise time although rounded at the top before it goes horizontal. Although upon adding the 100pF cap, I see zero idfference on the scope, the audible difference is crystal clear.

I don't have time to research this, but just musing, I wonder how clean a signal is needed for the input of the 4046 PLL? If it doesn't require a clean square wave, perhaps a proper integrator would be better circuit design. The output of the 4046 after it has gone through the 40103 counter is not a perfect square wave. But ar that point it doesn't need to be as it is simply feeding the gate or the base of the output transistor. I'm glad for that, as adding a flip-flop IC to this sized board to give it a clean square wave would have been pretty impossible.


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 Post subject: Re: Outputs treatment with a CD4060
PostPosted: Sep Sat 11, 2021 4:12 pm 
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...


Last edited by Dare4444 on Sep Sat 11, 2021 4:26 pm, edited 2 times in total.

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 Post subject: Re: Outputs treatment with a CD4060
PostPosted: Sep Sat 11, 2021 4:17 pm 
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CD4046 works just fine without flipflop. I always fed it direct from CD4060 for reference frequency. The spikes don't matter. The other input of CD4046 was fed with a CD4040. It's a versatile PLL device.


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 Post subject: Re: Outputs treatment with a CD4060
PostPosted: Sep Sat 11, 2021 4:25 pm 
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Mac, have you seen this synthesizer before? The output totem pole driver drives a MOSFET perfectly. I personally prefer CD4046. It's a foolproof device.


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 Post subject: Re: Outputs treatment with a CD4060
PostPosted: Sep Sat 11, 2021 9:36 pm 
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Interesting that this circuit version above has heavier filtering on pin 9 of the 4046 PLL where the main filter cap and anti-hunt R-C combination is. In my experience with PLL's, this is a very important filter, if the time constant is not long enough it can allow ripple in PLL control voltage and that frequency modulates the carrier, so it is a point worth checking, perhaps as an experiment increase the capacitor from pin 9 to 1uf and see if there is an effect or improvement or not.


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 Post subject: Re: Outputs treatment with a CD4060
PostPosted: Sep Sun 12, 2021 4:48 pm 
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ACORNVALVE wrote:
Interesting that this circuit version above has heavier filtering on pin 9 of the 4046 PLL where the main filter cap and anti-hunt R-C combination is. In my experience with PLL's, this is a very important filter, if the time constant is not long enough it can allow ripple in PLL control voltage and that frequency modulates the carrier, so it is a point worth checking, perhaps as an experiment increase the capacitor from pin 9 to 1uf and see if there is an effect or improvement or not.


I'm glad you bring this up. Sometime ago, maybe six months or a year, I experimented with the loop filter capacitor. The problem is I can't remember if it was on this board or another application where I use the 4046 and the 40103 that are configured as a 100X frequency multiplier.

Whichever, I recall ending up with loop filter capacitor right in the sweet spot. If I recall correctly, in these PLL loop filters, there's a trade-off between capture and hold, i.e. the range of frequencies that the filter can capture and how quickly it can acquire and hold the lock. So that capacitor needs to be deliberately chosen, sometimes as a compromise. In that experimentation I found out that the venerable CD4046 has a much wider effective range than some of the later PLL's that were supposed to have replaced it.

As I write this, its coming back that that sweet spot was found on the freq multiplier for that other use. It spans a wide range of four octaves, much more than we use in MW transmitting. With too large a cap, a sweep would peter out as it approached the top end. With too small a cap, the low end suffered. Although I don't have a specific memory I'm pretty certain that I'd have gone through the same procedure when developing the standalone frequency synthesizer board. I'm uncomfortable using a circuit without understanding how it works.

Because of that and because this transmitter is using the same PLL and counter values that have worked 100% before squeezing the traces so close together, I dont feel as much need to revisit it. Then again it's possible that this narrow two octave range is slid either too high or too low for the chosen cap, and then it's easy to add capacitance to check. To see if that would kill the noise, I'd need to desolder the 100pF cap that does the noise. Certainly this check can be made during beta testing. Thanks for the suggestion.


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